1.

X-masking for Deterministic In-System Tests / Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer (WIiT), Bartosz Włodarczak (WIiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2023, vol. 42, iss. 11, p. 4260-4269

Scientific article 100 2,7

2.

LBIST for Automotive ICs with Enhanced Test Generation / Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Łukasz Rybak, Jerzy Tyszer (WIiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2022, vol. 41, no. 7, p. 2290-2300

Scientific article 100 2,9

3.

DIST: Deterministic In-System Test with X-masking / Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer (WIiT), Bartosz Włodarczak (WIiT) // W: 2022 IEEE International Test Conference. ITC 2022. Proceedings: Institute of Electrical and Electronics Engineers Inc, 2022 - p. 20-27

Chapter in monograph / paper 20 70

4.

X-Masking for In-System Deterministic Test / Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer (WIiT), Bartosz Włodarczak (WIiT) // W: Proceedings of the IEEE European Test Symposium 2022: IEEE, 2022 - p. [1]-[6]

Chapter in monograph / paper 20

5.

Autonomous Scan Patterns for Laser Voltage Imaging / Jerzy Tyszer (WIiT), Wu-Tung Cheng, Sylwester Milewski (WIiT), Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka // IEEE Transactions on Emerging Topics in Computing - 2021, vol. 9, no. 2, p. 680-691

Scientific article 140 6,595

6.

X-Tolerant Compactor maXpress for In-System Test Applications with Observation Scan / Yingdi Liu, Sylwester Milewski (WIiT), Grzegorz Mrugalski, Nilanjan Mukherje, Janusz Rajski, Jerzy Tyszer (WIiT), Bartosz Włodarczak (WIiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2021, vol. 29, no. 8, p. 1553-1566

Scientific article 100 2,775

7.

Scan integrity tests for EDT compression / Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer (WIiT) // IEEE Design & Test - 2020, vol. 37, iss. 4, p. 21-26

Scientific article 70 1,527

8.

Test Sequence-Optimized BIST for Automotive Applications / Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Łukasz Rybak, Jerzy Tyszer (WIiT) // W: IEEE European Test Symposium (ETS) 2020: IEEE, 2020

Chapter in monograph / paper 20

9.

X-Tolerant Tunable Compactor for In-System Test / Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherje, Janusz Rajski, Jerzy Tyszer (WIiT), Bartosz Włodarczak (WIiT) // W: IEEE International Test Conference (ITC) 2020: IEEE, 2020

Chapter in monograph / paper 20 70

10.

On cyclic scan integrity tests for EDT-based compression / Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer (WEiT) // W: IEEE 37th VLSI Test Symposium (VTS 2019): IEEE, 2019

Chapter in monograph / paper 20

11.

Star-EDT: Deterministic on-chip scheme using compressed test patterns / Grzegorz Mrugalski, Janusz Rajski, Łukasz Rybak, Jędrzej Solecki, Jerzy Tyszer (WEiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2017, vol. 36, no. 4, p. 683-693

Scientific article 25 2,089

12.

Trimodal scan-based test paradigm / Jerzy Tyszer (WEiT), Grzegorz Mrugalski, Janusz Rajski, Jędrzej Solecki, Chen Wang // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2017, vol. 25, no. 3, p. 1112-1125

Scientific article 30 1,744

13.

A deterministic BIST scheme based on EDT-compressed test patterns / Grzegorz Mrugalski, Janusz Rajski, Łukasz Rybak, Jędrzej Solecki (WEiT), Jerzy Tyszer (WEiT) // W: IEEE International Test Conference (ITC), Anaheim, CA, 6-8 October 2015: IEEE, 2015 - p. 1-8

Paper

14.

Low-Power Programmable PRPG With Test Compression Capabilities / Michał Filipek (WEiT), Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jędrzej Solecki (WEiT), Jerzy Tyszer (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2015, vol. 23, no. 6, p. 1063-1076

Scientific article 30 1,245

15.

Scan test bandwidth management for ultra-large-scale multicore architectures / Wu-Tung Cheng, Yan Dong, Grady Gilles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2015, vol. 23, no. 6, p. 1050-1062

Scientific article 30 1,245

16.

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures / Wu-Tung Cheng, Yan Dong, Grady Gilles, Yu Huang, Jakub Janicki (WEiT), Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2015, vol. 23, no. 6, p. 1050-1062

Scientific article 30 1,245

17.

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm / Grzegorz Mrugalski, Janusz Rajski, Jędrzej Solecki (WEiT), Jerzy Tyszer (WEiT), Chen Wang // W: IEEE 24th Asian Test Symposium (ATS), Mumbai, India, 22-25 November 2015: IEEE, 2015 - p. 19-24

Paper

18.

High-speed serial embedded deterministic test for system-on-chip designs / Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel (WEiT), Janusz Rajski, Jakub Janicki, Jerzy Tyszer (WEiT) // W: IEEE 23rd Asian Test Symposium (ATS), 2014, Hangzhou, 16-19 Nov. 2014: IEEE, 2014 - p. 74-80

Paper

19.

Low Power Test Compression with Programmable Broadcast-Based Control / Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer (WEiT) // W: IEEE 23rd Asian Test Symposium (ATS), 2014, Hangzhou, 16-19 Nov. 2014: IEEE, 2014 - p. 174-179

Paper

20.

On using implied values in EDT-based test compression / Marcin Gębala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // W: 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, San Francisco, CA, 1-5 June 2014: IEEE, 2014 - p. 1-6

Paper

21.

New test compression scheme based on low power BIST / Jerzy Tyszer (WEiT), Michał Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski // W: 18th IEEE European Test Symposium (ETS 2013), Avignon, 27-30 May 2013: IEEE, 2013 - p. 1-6

Paper

22.

On deploying scan chains for data storage in test compression environment / Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Design and Test of Computers - 2013, vol. 30, iss. 1, p. 68-76

Scientific article 30

23.

Test Time Reduction in EDT Bandwidth Management for SoC Designs / Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2013, vol. 32, no. 11, p. 1776-1786

Scientific article 25 1,203

24.

Bandwidth-aware test compression logic for SoC designs / Jakub Janicki, Jerzy Tyszer (WEiT), Grzegorz Mrugalski, Janusz Rajski // W: IEEE 17th European Test Symposium - Los Almitos, California, United States : IEEE Computer Society, 2012 - p. 14-19

Paper

25.

EDT Bandwidth Management in SoC Designs / Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2012, vol. 31, no. 12, p. 1894-1907

Scientific article 1,093

26.

High performance dense ring generators / Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Computers - 2006, vol. 55, no. 1, p. 83-87

Scientific article 1,426

27.

Test response compactor with programmable selector / Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer (WEiT) // W: 43rd ACM/IEEE Design Automation Conference : San Francisco, CA, July 24-28, 2006 - New York, USA : IEEE, 2006 - p. 1089-1094

Paper

28.

X-press compactor for 1000x reduction of test data / Janusz Rajski, Jerzy Tyszer (WEiT), Grzegorz Mrugalski, Nilanjan Mukherjee, Wu-Tung Cheng, Mark Kassab // W: IEEE International Test Conference ITC 2006 : Santa Clara, 22-27 October 2006: IEEE, 2006 - p. 18.1-1-18.1-10

Paper

29.

Fault diagnosis in designs with convolutional compactors / Grzegorz Mrugalski (WE), Artur Pogiel (WE), Janusz Rajski, Jerzy Tyszer (WE), Chen Wang // W: International Test Conference 2004 : Proceedings: IEEE, 2004 - p. 498-507

Paper

30.

Ring generators - new devices for embedded test applications / Grzegorz Mrugalski (WE), Janusz Rajski, Jerzy Tyszer (WE) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2004, vol. 23, iss. 9, p. 1306-1320

Scientific article 0,913

31.

Układy cyfrowe : zbiór zadań z rozwiązaniami / Jerzy Tyszer (WE), Grzegorz Mrugalski (WE) / Poznań, Polska : Wydawnictwo Politechniki Poznańskiej, 2004 - 266 s.

Scholarly textbook / script

32.

2D test sequence generators / Grzegorz Mrugalski (WE), Janusz Rajski, Jerzy Tyszer (WE) // IEEE Design and Test of Computers - 2003, vol. 20, iss. 1, p. 51-59

Scientific article

33.

Dense ring generators of pseudo-random test patterns / Grzegorz Mrugalski (WE), Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WE) // W: Sixth International IEEE Workshop on Design and diagnostics of electronic circuits and systems, Poznań, Poland, April 14-16, 2003 : proceedings - Poznań, Polska : Wydawnictwo Politechniki Poznańskiej, 2003 - p. 64-72

Paper

34.

High speed ring generators and compactors of test data [logic IC test] / Grzegorz Mrugalski (WE), Janusz Rajski, Jerzy Tyszer (WE) // W: Proceedings 21st IEEE VLSI Test Symposium: IEEE, 2003 - p. 57-62

Paper

35.

Embedded deterministic test for low cost manufacturing test / Janusz Rajski, Jerzy Tyszer (WE), Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski (WE), Geir Eide, Jun Qian // W: Proceedings International Test Conference 2002 - Piscataway, United States : IEEE, 2002 - p. 301-310

Paper

36.

Układy cyfrowe : zbiór zadań z rozwiązaniami / Jerzy Tyszer (WE), Grzegorz Mrugalski (WE) / Poznań, Polska : Wydawnictwo Politechniki Poznańskiej, 2002 - 266 s.

Scholarly textbook / script