SIS PUT | no. 6 | vol. 38 | 2019 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Logic BIST with capture-per-clock hybrid test points / Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WEiT), Justyna Zawada // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2019, vol. 38, no. 6, p. 1028-1041

Scientific article 100 2,168