Title
Implementation of the Conscience Mechanism for Kohonen's Neural Network in CMOS 0.18 μm Technology
Authors
[ 1 ] Katedra Sterowania i Inżynierii Systemów (KI), Wydział Informatyki i Zarządzania, Politechnika Poznańska | [ P ] employee
Year of publication
2006
Chapter type
paper
Publication language
english
Keywords
EN
- artificial neural networks
- conscience mechanism
- unsupervised learning on silicon
- CMOS analog circuits
- low power circuits
Abstract
EN Hardware implementation of the conscience mechanism in Kohonen’s neural networks is presented in this work. The conscience mechanism is an important component of the neural network as it eliminates so called dead neurons leading to larger network efficiency and smaller quantization error. The conscience mechanism itself and Winner Take All (WTA) block have been implemented in 0.18 μm CMOS process. The design integrated circuit (IC) is a continuation of the earlier effort to produce elements required to implement competitive learning mechanisms in neural networks as presented in [4, 5, 6, 7, 12, 18]. The conscience mechanism circuit occupies 270 μm2 and dissipates maximum power of 22 μW at 2V power supply. The WTA block occupies 0.02 mm2 and dissipates 50 μW.
Pages (from - to)
310 - 315
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