Title
Low power, low chip area, digital distance calculation circuit for self-organizing neutral networks realized in the CMOS technology
Authors
[ 1 ] Katedra Inżynierii Komputerowej, Wydział Informatyki, Politechnika Poznańska | [ P ] employee
Year of publication
2013
Published in
Article type
scientific article
Publication language
english
Pages (from - to)
247 - 252
Ministry points / journal
10
System created by Poznań University of Technology
and Poznan Supercomputing and Networking Center
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