2005

paper

english

EN The H.264/AVC is the most recent standard of video compression. In this paper original and flexible architecture of image reconstruction block for H.264/AVC decoder is presented. Depending on application requirements the proposed design may be configured as low complexity simple unit with good performance or as fully pipelined construction with high performance. The architecture was implemented in Verilog HDL and synthesized and then tested on Xilinx VirtexII family device. The simulation results indicate that the implemented circuit is capable to process real-time video at clock close to the image sampling frequency.

I/217 - I/221

10.1109/ECCTD.2005.1522949

https://ieeexplore.ieee.org/document/1522949

Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork Ireland, August 29th - September 1st 2005

European Conference on Circuit Theory and Design, ECCTD 2005, 28.08.2005 - 02.09.2005, Cork, Ireland