Depending on the amount of data to process, file generation may take longer.

If it takes too long to generate, you can limit the data by, for example, reducing the range of years.

Article

Download BibTeX

Title

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Authors

[ 1 ] Instytut Informatyki, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | [ S ] student | [ P ] employee

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

Year of publication

2023

Published in

Electronics

Journal year: 2023 | Journal volume: vol. 12 | Journal number: iss. 20

Article type

scientific article

Publication language

english

Keywords
EN
  • VLSI
  • TinyML
  • wearable devices
  • power-efficient architecture
  • model hyperparameters
Abstract

EN The growing popularity of edge computing goes hand in hand with the widespread use of systems based on artificial intelligence. There are many different technologies used to accelerate AI algorithms in end devices. One of the more efficient is CMOS technology thanks to the ability to control the physical parameters of the device. This article discusses the complexity of the semiconductor implementation of TinyML edge systems in relation to various criteria. In particular, the influence of the model parameters on the complexity of the system is analyzed. As a use case, a CMOS preprocessor device dedicated to detecting heart rate in wearable devices is used. The authors use the current and weak inversion operating modes, which allow the preprocessor to be powered by cells of the human energy harvesting class. This work analyzes the influence of tuning hyperparameters of the learning process on the performance of the final device. This article analyzes the relationships between the model parameters (accuracy and neural network size), input data parameters (sampling rates) and CMOS circuit parameters (circuit area, operating frequency and power consumption). Comparative analyses are performed using TSMC 65 nm CMOS technology. The results presented in this article may be useful to direct this work with the model in terms of the final implementation as the integrated circuit. The dependencies summarized in this work can also be used to initially estimate the costs of the hardware implementation of the model.

Date of online publication

17.10.2023

Pages (from - to)

4291-1 - 4291-19

DOI

10.3390/electronics12204291

URL

https://www.mdpi.com/2079-9292/12/20/4291

Comments

Article number: 4291

License type

CC BY (attribution alone)

Open Access Mode

open journal

Open Access Text Version

final published version

Date of Open Access to the publication

at the time of publication

Ministry points / journal

140

Impact Factor

2,6

This website uses cookies to remember the authenticated session of the user. For more information, read about Cookies and Privacy Policy.