Structure and Principles of Operation of a Quaternion VLSI Multiplier

Aleksandr Cariow; Mariusz Naumowicz; Andrzej Handkiewicz

doi:10.3390/app14188123

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Title

Structure and Principles of Operation of a Quaternion VLSI Multiplier

Authors

Aleksandr Cariow
Mariusz Naumowicz (WIiT) ^{[ 1 ][ 2.3 ][ P ]}
Andrzej Handkiewicz

^{[ 1 ]} Instytut Informatyki, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | ^{[ P ]} employee

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

Year of publication

2024

Published in

Applied Sciences

Journal year: 2024 | Journal volume: vol. 14 | Journal number: iss. 18

Article type

scientific article

Publication language

english

Keywords

EN

hypercomplex numbers
quaternion multiplier
fast algorithm
matrix–vector multiplication
hardware implementation
FPGA
ASIC

Abstract

EN The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.

Date of online publication

10.09.2024

Pages (from - to)

8123-1 - 8123-13

DOI

10.3390/app14188123

URL

https://www.mdpi.com/2076-3417/14/18/8123

Comments

Article Number: 8123

License type

CC BY (attribution alone)