Processing may take a few seconds...

Article


Title

RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA

Authors

[ 1 ] Katedra Telekomunikacji Multimedialnej i Mikroelektroniki, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

Year of publication

2019

Published in

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Journal year: 2019 | Journal volume: vol. 27 | Journal number: no. 6

Article type

scientific article

Publication language

english

Keywords
EN
  • distributed memory
  • lookup table RAM(LUTRAM)
  • fairness
  • field-programmable gate array (FPGA)
  • network-on-chip (NoC)
  • virtual cut-through
Pages (from - to)

1284 - 1297

DOI

10.1109/TVLSI.2019.2899575

URL

https://ieeexplore.ieee.org/document/8663289

Points of MNiSW / journal

100.0

Points of MNiSW / journal in years 2017-2021

100.0

Impact Factor

2.037

This website uses cookies to remember the authenticated session of the user. For more information, read about Cookies and Privacy Policy.