2006

referat

angielski

EN The paper presents a new and efficient architecture for H.264/AVC video encoder control. The architecture of mode decision and cost estimation module is implemented with the use of bit-serial arithmetic and provides pipelined processing of image blocks. The module is designed to support FPGA devices. It has been shown that the design is capable to perform at a very low clock speed, thus it is a suitable solution for wireless communications. The proposed modules have been implemented in Verilog HDL and synthesized for a Xilinx Virtex II family device.

3842 - 3845

10.1109/ISCAS.2006.1693466

https://ieeexplore.ieee.org/document/1693466

Dokument elektroniczny

ISCAS 2006 : 2006 IEEE International Symposium on Circuits and Systems : Circuits and systems : at crossroads of life and technology : proceedings : 21-24 May 2006, Island of Kos, Greece

2006 IEEE International Symposium on Circuits and Systems ISCAS 2006, 21-24.05.2006, Kos Island, Greece