FPGA chip as a system master hardware aided parallel computing
[ 1 ] Katedra Inżynierii Komputerowej (KIk), Wydział Informatyki i Zarządzania, Politechnika Poznańska | [ 2 ] Instytut Automatyki i Inżynierii Informatycznej, Wydział Elektryczny, Politechnika Poznańska | [ P ] pracownik
2006
referat
angielski
EN This paper presents prototype board and its operating system dedicated for application specific parallel processing. The proposed architecture consists of two AVR microprocessors, FPGA Spartan3, SRAM and Flash EEPROM Memories, DA converters, and several serial communication ports. To make the system "designer friendly" a supervising algorithm, which can be called as a kind of "operating system" was elaborated. The algorithms were described in VHDL. The Spartan3 FPGA was chosen as a target platform to implement the master controller for the system. Necessary IO devices’ controllers were implemented in AVRmicro. The designed board with elaborated libraries provides convenient solution to develop dedicated parallel processing systems.
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