Structure and Principles of Operation of a Quaternion VLSI Multiplier
[ 1 ] Instytut Informatyki, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | [ P ] pracownik
2024
artykuł naukowy
angielski
- hypercomplex numbers
- quaternion multiplier
- fast algorithm
- matrix–vector multiplication
- hardware implementation
- FPGA
- ASIC
EN The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.
10.09.2024
8123-1 - 8123-13
Article Number: 8123
CC BY (uznanie autorstwa)
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