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Dissertation

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Title

Real Time Hardware Architectures of Selected MPEG-7 Descriptors

Authors

Rafał Kapela ^{[ 1 ][ P ]}

^{[ 1 ]} Katedra Inżynierii Komputerowej (KIk), Wydział Informatyki i Zarządzania, Politechnika Poznańska | ^{[ P ]} employee

Promoter

Andrzej Rybarczyk ^{[ 1 ][ P ]}

^{[ 1 ]} Katedra Inżynierii Komputerowej (KIk), Wydział Informatyki i Zarządzania, Politechnika Poznańska | ^{[ P ]} employee

Reviewers

Andrzej Napieralski
Andrzej Urbaniak ^{[ 1 ][ P ]}

^{[ 1 ]} Instytut Informatyki (II), Wydział Informatyki i Zarządzania, Politechnika Poznańska | ^{[ P ]} employee

Title variant

PL Sprzętowe architektury czasu rzeczywistego wybranych deskryptorów MPEG-7

Language

english

Abstract

EN The thesis presents hardware realizations of chosen MPEG-7 visual descriptors and their possible usage in number of real-time or on-line video content MPEG-7-based description systems. Mentioned realizations could work as both: stand-alone or embedded systems. The hardware description language was VHDL. In order to compare the architectures with software realizations the descriptors' algorithms were implemented in MATLAB or C++. The algorithms of MPEG-7 visual descriptors were synthesized into a Xilinx Virtex V1000 target Field Gate Programmable Array (FPGA) platform. Chapter 3 presents synthesis results obtained for VHDL and, if available, Handel-C based hardware descriptions, as well as their comparison with software realizations by means of computational speed, power consumption and FPGA resources utilization. Moreover, the descriptors efficiency is also investigated according to the MPEG-7 standard Color Core Experiments (CCE) and purposely created image data bases for particular efficiency tests. One of most interesting realizations of descriptors hardware realizations is the Real-time Visual Description System presented in Chapter 4. In this project the searching task was divided into two parts. The first one is the descriptors extraction. Next, the second part uses the descriptors' values in a particular searching algorithm. The proposed system architecture could be used for real-time video indexing and retrieval, content summarization, content delivery, surveillance, personalized services, etc. Descriptors' extractor IP core designed for ASIC realization in CMOS 0.35um is proposed. The proposed hardware architecture splits the computational burden into several processes where calculations are made simultaneously in order to improve system's speed. These methods make hardware realizations of main computational-consuming modules of the system more time and power efficient. Four different hardware architectures are discussed. The usage of the IP cores is illustrated in the VCDS, where new searching algorithms are implemented. Experimental results prove the effectiveness of the hardware architectures and the new approach to the similarity based searching methods. The work is concluded by Chapter 5 where possible scenarios of hardware realizations usage are presented. The implementations include stationary, as well as mobile devices. At the end some summary of the work is presented.

Number of pages

137

Signature of printed version

DrOIN 1063

On-line catalog

to2008

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