Step response sensitivity of VLSI Interconnects

Agnieszka Wardzińska; Wojciech Bandurski

doi:10.1109/SaPIW.2013.6558349

Scientific Information System of the Poznań University of Technology

PL EN

Main page / Publications / Step response sensitivity of VLSI Interconnects

Submit a comment

Chapter

Download BibTeX

Title

Step response sensitivity of VLSI Interconnects

Authors

Agnieszka Wardzińska (WEiT) ^{[ 1 ][ P ]}
Wojciech Bandurski (WEiT) ^{[ 1 ][ P ]}

^{[ 1 ]} Katedra Telekomunikacji Multimedialnej i Mikroelektroniki, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | ^{[ P ]} employee

Year of publication

2013

Chapter type

paper

Publication language

english

Keywords

EN

VLSI interconnect
RLC transmission line
sensitivity
step response

Abstract

EN In the paper sensitivity of the voltage step response of the system inverter-interconnect-inverter with respect to selected parameters is considered. The sensitivity coefficients for normalized parameters are given. These formulas correspond with sensitivity coefficients to interconnect RLC parameters and input and output parameters. The sensitivity is calculated directly from step response formula. The closed form formula for the output response allows to present closed form formulas the for sensitivity.

Pages (from - to)

1 - 4

DOI

10.1109/SaPIW.2013.6558349

URL

https://ieeexplore.ieee.org/document/6558349

Book

17th IEEE Workshop on Signal and Power Integrity (SPI), Paris, 12-15 May, 2013

Presented on

17th IEEE Workshop on Signal and Power Integrity (SPI), 12-15.05.2013, Paris, France

Publication indexed in

WoS (15)

System created by Poznań University of Technology and Poznan Supercomputing and Networking Center

Log in through eKonto to add to SIS