2014

paper

english

EN This paper describes the design of a current-mode, active-passive second-order, continuous-time Sigma-Delta Modulator(ΣΔM). The proposed ΣΔM uses a single continuous-time current-mode integrator combined with low-pass passive filter topology. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 400 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 60.7 dB and a dynamic range(DR) of 65 dB while dissipating 132 μW which corresponds to an efficiency of 37.3 fJ/conv. The proposed architecture allows to obtain the best compromise between power consumption and performance of the ADC.

117 - 120

10.1109/MIXDES.2014.6872168

https://ieeexplore.ieee.org/document/6872168

MIXDES 2014, 21st International Conference "Mixed Design of Integrated Circuits and Systems", Lublin, June 19-21, 2014

21st International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2014, 19-21.06.2014, Lublin, Polska

WoS (15)