FPGA implementation of the MMRRS scheduling algorithm for VOQ switches
[ 1 ] Katedra Sieci Telekomunikacyjnych i Komputerowych, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee
2010
paper
english
- scheduling algorithms
- Virtual Output Queuing
- packet switching
EN In this article, a FPGA implementation of the Maximal Matching with Round-Robin Selection (MMRRS) scheduling algorithm for Virtual Output Queuing (VOQ) switches is presented. Implementation is done in the VERILOG hardware description language. The results results obtained from the software model simulation and hardware implementation in XILINX Virtex 5 proved that the implementation is correct. The greatest achievement is the optimization of the scheduler, with the time needed for decision - taking being three clock cycles independent of switch size. The simplicity of the MMRRS algorithm makes the scheduler a simple structure which is not complicated to implement.