Depending on the amount of data to process, file generation may take longer.

If it takes too long to generate, you can limit the data by, for example, reducing the range of years.

Chapter

Download BibTeX

Title

Automated design and layout generation for switched current circuits

Authors

[ 1 ] Katedra Inżynierii Komputerowej (KIk), Wydział Informatyki i Zarządzania, Politechnika Poznańska | [ P ] employee

Year of publication

2006

Chapter type

paper

Publication language

english

Abstract

EN Recent advances in VLSI technology in combinations with economical motivations results in drive to integrate the complete signal processing chain on a single ASIC or SOC. However, the luck of supporting CAD tools for the synthesis and layout generation of the analog blocks is the major bottleneck in the design of modern mixed signal VLSI circuits. The paper presents original methods and their implementation for automated design of the switched current (SI) blocks. The design flow includes programs for SI circuits synthesis and automated layout generation. As an example a design of current mirrors for SI filters is presented.

Pages (from - to)

637 - 640

DOI

10.1109/ISCAS.2006.1692666

URL

https://ieeexplore.ieee.org/document/1692666

Comments

Dokument elektroniczny

Book

ISCAS 2006 : 2006 IEEE International Symposium on Circuits and Systems : Circuits and systems : at crossroads of life and technology : proceedings : 21-24 May 2006, Island of Kos, Greece

Presented on

2006 IEEE International Symposium on Circuits and Systems ISCAS 2006, 21-24.05.2006, Kos Island, Greece

This website uses cookies to remember the authenticated session of the user. For more information, read about Cookies and Privacy Policy.