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Chapter

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Title

Elements of Architecture of Simulator Realized on NetFPGA10G Card

Authors

[ 1 ] Instytut Sieci Teleinformatycznych, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

Year of publication

2022

Chapter type

chapter in monograph / paper

Publication language

english

Keywords
EN
  • application specific integrated circuits
  • computer architecture
  • telecommunication traffic
  • programming
  • software
  • Central Processing Unit
  • integrated circuit modeling
Abstract

EN Simulations in typical software take a long time. To make them faster, it is possible to use hardware acceleration. Some people use graphical processors (GPU) which are faster than typical CPU (Central Processing Unit). Much more faster and more effective is to prepare Application Specific Integrated Circuit (ASIC). But it costs a lot of money and also takes time. Nowadays, optimal solution is to use FPGA chips (Field-Programmable Gate Array) which allow to prepare programmable hardware. It is flexible and fast. It requires specific treatment, tool chain for programming and testing, but finally, it gives powerful platform for calculation and data processing. In this paper I will show elements of architecture of system which was composed of 5 NetFPGA cards with 10G interfaces and Virtex 5 onboard (FPGA chip from Xilinx). Primary purpose of such a card is to serve Ethernet/IP network traffic, but, after preparing dedicated design, it is possible to use it as a hardware engine for calculations, ie. simulations.

Pages (from - to)

1 - 2

DOI

10.1109/ICCCN54977.2022.9868941

URL

https://ieeexplore.ieee.org/document/9868941

Book

2022 International Conference on Computer Communications and Networks (ICCCN)

Presented on

31st International Conference on Computer Communications and Networks, ICCCN 2022, 25-27.07.2022, Honolulu, United States

License type

other

Ministry points / chapter

20

Ministry points / conference (CORE)

140

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