Three New Approaches to Command Handling in NetFPGA Hardware Simulators with Custom Internal Architecture
[ 1 ] Instytut Sieci Teleinformatycznych, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | [ P ] employee
2023
chapter in monograph / paper
english
- NetFPGA
EN Simulations in typical software take a long time. To make them faster, it is possible to use hardware acceleration. Some people use graphical processors (GPU) which are faster than typical CPU (Central Processing Unit). Much more faster and more effective is to prepare Application Specific Integrated Circuit (ASIC). But it costs a lot of money and also takes time. Nowadays, optimal solution is to use FPGA chips (Field-Programmable Gate Array) which allow to prepare programmable hardware. It is flexible and fast. It requires specific treatment, tool chain for programming and testing, but finally, it gives powerful platform for calculation and data processing. In this paper I will show treatment of new architecture in terms of command handling. Commands are sent to hardware as IP packets and after calculation results should be collected. There are at least 3 ways for this.
210 - 215
5
70