SIS PUT | VLSI Testing – Design for test part 2

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Works title

VLSI Testing – Design for test part 2

Authors

Jerzy Tyszer (WIiT) ^{[ 1 ][ P ]}

^{[ 1 ]} Instytut Radiokomunikacji, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | ^{[ P ]} employee

Work ID

r916_2020

Keywords

PL

test generation
design for testability

Date

04.05.2020

Language

english

Number of pages or volume of work

21

Type of work

educational materials

System created by Poznań University of Technology and Poznan Supercomputing and Networking Center

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