FPGA controller for rearrangeable Log2(N, 0, p) fabrics with an even number of stages
[ 1 ] Katedra Sieci Telekomunikacyjnych i Komputerowych, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee
2011
paper
english
EN In this paper we present rearrangeable log 2 (N, 0, p) switching fabrics and the control algorithm for the case of an even number of stages. The main topic of this paper is the implementation of a hardware controller for such fabrics. The algorithm is described in VHDL code and realized in ML505 - the demo board for Virtex 5 - FGPA chip from the Xilinx Company. The implementation presented here works very fast, the controller can send out the set of actual signals just 20 nanoseconds after the request has been made.
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