The Design of a Compact LIF-Neuron circuit in FPGA to Enable Implementation of large-scale spiking neuron networks with learning capabilities
[ 1 ] Instytut Automatyki i Inżynierii Informatycznej, Wydział Elektryczny, Politechnika Poznańska | [ P ] employee
2006
paper
english
EN Digital implementation of the single Leaky-Integrate and Fire (LIF) neuron model is proposed. Simplifying assumptions are introduced and justified , leading to solution, which is compact but still preserving the essential properties of the model. As a result, the relatively large-scale Spiking Neural Network (SNN) architectures can be configure with the proposed neuron implementation on available FPGA matrices. A slight extension to the neuron circuit is proposed in order to enable a supervised learning of the network configurred of such elements. The learning method has been already described in [7]. VHDL codes defining the neuron architecture is provided. Included diagrams illustrate the relationship between the single neuron architecture, its parametrical properties and the amount of the FPGA resources involved.
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