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Implementation of fast uniform random number generator on FPGA


[ 1 ] Instytut Automatyki i Inżynierii Informatycznej, Wydział Elektryczny, Politechnika Poznańska | [ 2 ] Instytut Elektrotechniki i Elektroniki Przemysłowej, Wydział Elektryczny, Politechnika Poznańska | [ D ] phd student | [ P ] employee

Year of publication


Published in

Poznan University of Technology Academic Journals. Electrical Engineering

Journal year: 2014 | Journal number: Issue 80

Article type

scientific article

Publication language


  • random number generator
  • uniform noise
  • FPGA unit
  • logic functions

EN The article presents approach to implementation of random number generator on FPGA unit. The objective was to select a generator with good properties (correlation values and matching of probability density function were taken into account). Design focused on logical elements so that the pseudo-random number generation time depend only on the electrical properties of the system. The results are positive, because the longest time determining the pseudorandom number was 16.7ns for the “slow model” of the FPGA and 7.3ns for “fast model”, while one clock cycle lasts 20ns.

Pages (from - to)

167 - 173

Presented on

Computer Applications in Electrical Engineering 2014, 28-29.04.2014, Poznań, Polska

Ministry points / journal


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