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Article

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Title

Hardware Protection via Logic Locking Test Points

Authors

[ 1 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee | [ D ] phd student

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

Year of publication

2018

Published in

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal year: 2018 | Journal volume: vol. 37 | Journal number: no. 12

Article type

scientific article

Publication language

english

Keywords
EN
  • design for testability
  • embedded test
  • hardware security
  • logic locking
  • scan-based testing
  • test points
Date of online publication

02.02.2018

Pages (from - to)

3020 - 3030

DOI

10.1109/TCAD.2018.2801240

URL

https://doi.org/10.1109/TCAD.2018.2801240

Ministry points / journal

25

Ministry points / journal in years 2017-2021

25

Impact Factor

2,402

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