A Low-Complexity Start–Stop True Random Number Generator for FPGAs

Łukasz Matuszewski; Mieczysław Jessa

doi:10.3390/app14135642

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Title

A Low-Complexity Start–Stop True Random Number Generator for FPGAs

Authors

Łukasz Matuszewski (WIiT) ^{[ 1 ][ 2.3 ][ P ]}
Mieczysław Jessa (WIiT) ^{[ 1 ][ 2.3 ][ P ]}

^{[ 1 ]} Instytut Telekomunikacji Multimedialnej, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | ^{[ P ]} employee

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

Year of publication

2024

Published in

Applied Sciences

Journal year: 2024 | Journal volume: vol. 14 | Journal number: iss. 13

Article type

scientific article

Publication language

english

Keywords

EN

random number generator
true randomness
ring oscillators
entropy
restarts
statistical tests
FPGA

Abstract

EN This paper introduces a low-complexity start–stop true random number generator (TRNG) utilizing jitter in ring oscillators (ROs). Incorporating phase detectors enhances entropy extraction from the same number of ROs. The raw bits undergo online post-processing using the SHA-1 algorithm, which is widely supported by many programming languages. The output bit streams pass all NIST statistical tests (SP 800-22 and SP-90B). Bits are generated on demand, enhancing security by preventing eavesdropping during continuous bit production. The TRNG maintains its performance regardless of the FPGA manufacturer.

Pages (from - to)

5642-1 - 5642-11

DOI

10.3390/app14135642

URL

https://www.mdpi.com/2076-3417/14/13/5642

Comments

Article number: 5642

License type

CC BY (attribution alone)

Open Access Mode

open journal