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Embedded deterministic test


[ 1 ] Instytut Elektroniki i Telekomunikacji (IEt), Wydział Elektryczny, Politechnika Poznańska | [ P ] employee

Year of publication


Published in

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal year: 2004 | Journal volume: vol. 23 | Journal number: iss. 5

Article type

scientific article

Publication language


  • design for testability (DFT)
  • linear finite state machines
  • manufacturing test
  • test application time reduction
  • test data volume compression

EN This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

Pages (from - to)

776 - 792




Impact Factor


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