2023

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Rocznik: 2023 | Tom: vol. 42 | Numer: iss. 11

artykuł naukowy

angielski

EN Deterministic in-system tests begin to play an essential role in safety-critical applications, in large data centers, or in monitoring silicon aging, to name just a few. All of these ecosystems require periodic, high-quality tests to assure required test coverage and short test application, especially in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multimillion-bit test responses with unknown (X) values to small signatures. This, in turn, allows for a much faster input-only streaming and a simultaneous reduction of the on-chip-stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This paper presents a user-tunable X-masking scheme. It works synergistically with on-chip test compression logic by employing encoded test data to completely filter out unknown values that otherwise might reach a test response compactor such as a MISR or test result sticky-bits used by the on-chip compare framework. It makes the proposed scheme a very versatile of its kind. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on various test-related statistics.

4260 - 4269

10.1109/TCAD.2023.3261781

https://ieeexplore.ieee.org/document/10080973?source=authoralert

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