Title
On Test Points Enhancing Hardware Security
Authors
[ 1 ] Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee | [ D ] phd student
Year of publication
2016
Chapter type
paper
Publication language
english
Abstract
EN Recent reverse-engineering attempts to steal a competitive design intellectual property (IP) or to identify the device technology in order to counterfeit integrated circuits (ICs) have raised serious concerns in the IC design community. This paper demonstrates that test points - industry-proven design-for-test technology used to enhance the overall design testability - can also be deployed in the mission mode to obfuscate the circuit's structure, and thus to improve the hardware security against reverse engineering, IC cloning, and IP theft. In particular, it is shown how test points can facilitate the hiding of design functionality from adversaries. As a result, not only the overall design testability is improved, but also effective protection against reverse engineering and other forms of attacks is ensured.
Pages (from - to)
61 - 66
Publication indexed in
WoS (15)
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