High speed ring generators and compactors of test data [logic IC test]

Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer

doi:10.1109/VTEST.2003.1197633

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Title

High speed ring generators and compactors of test data [logic IC test]

Authors

Grzegorz Mrugalski (WE) ^{[ 1 ][ P ]}
Janusz Rajski
Jerzy Tyszer (WE) ^{[ 1 ][ P ]}

^{[ 1 ]} Instytut Elektroniki i Telekomunikacji (IEt), Wydział Elektryczny, Politechnika Poznańska | ^{[ P ]} employee

Year of publication

2003

Chapter type

paper

Publication language

english

Abstract

EN This paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial.

Pages (from - to)

57 - 62

DOI

10.1109/VTEST.2003.1197633

URL

https://ieeexplore.ieee.org/document/1197633

Book

Proceedings 21st IEEE VLSI Test Symposium

Presented on

21st IEEE VLSI Test Symposium, 01.05.2003, Napa, USA

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