Design for low test pattern counts
[ 1 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ 2 ] Dziekanat Wydziału Elektroniki i Telekomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee
2015
paper
english
- Design for testability
- scan-based test
- test data compression
EN This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x – 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.
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