SIS PUT | Universal compactor architecture for testing circuits

Scientific Information System of the Poznań University of Technology

PL EN

Main page / IP outcomes / Universal compactor architecture for testing circuits

Submit a comment

Outcome

Title

Universal compactor architecture for testing circuits

Creators

Jerzy Tyszer (WIiT) ^{[ 1 ][ 2.3 ][ P ]}
Yingdi Liu
Nilanjan Mukherjee
Janusz Rajski
Grzegorz Mrugalski
Bartosz Włodarczak (WIiT) ^{[ 2 ][ SzD ]}

^{[ 1 ]} Instytut Radiokomunikacji, Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | ^{[ 2 ]} Wydział Informatyki i Telekomunikacji, Politechnika Poznańska | ^{[ P ]} employee | ^{[ SzD ]} doctoral school student

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

PAT number

Z/11/2023

Type of protection law

invention

Submission, granting and maintenance of protection

Outcome protection

Stany Zjednoczone

Submission to the Patent Office

Patent Office submission number

17753332

Patent office submission date

06.09.2019

Country / region

Stany Zjednoczone

Granting and maintaining protection

Protection law number

11815555

Date of obtaining the right

14.11.2023

Country / region

Stany Zjednoczone

System created by Poznań University of Technology and Poznan Supercomputing and Networking Center