Depending on the amount of data to process, file generation may take longer.

If it takes too long to generate, you can limit the data by, for example, reducing the range of years.

Chapter

Download BibTeX

Title

High-speed serial embedded deterministic test for system-on-chip designs

Authors

[ 1 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Year of publication

2014

Chapter type

paper

Publication language

english

Abstract

EN The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.

Pages (from - to)

74 - 80

DOI

10.1109/ATS.2014.25

URL

https://ieeexplore.ieee.org/document/6979080

Book

IEEE 23rd Asian Test Symposium (ATS), 2014, Hangzhou, 16-19 Nov. 2014

Presented on

IEEE 23rd Asian Test Symposium (ATS), 2014, 16-19.11.2014, Hangzhou, China

This website uses cookies to remember the authenticated session of the user. For more information, read about Cookies and Privacy Policy.