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EDT Bandwidth Management in SoC Designs


[ 1 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Year of publication


Published in

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal year: 2012 | Journal volume: vol. 31 | Journal number: no. 12

Article type

scientific article

Publication language


  • bandwidth management
  • embedded deterministic test
  • low pin-count testing
  • scan-based test
  • test access mechanism
  • test compression
  • test scheduling

EN This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

Pages (from - to)

1894 - 1907




Impact Factor


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