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High level synthesis in FPGA of TCS/RNS converter


Rok publikacji


Opublikowano w

Poznan University of Technology Academic Journals. Electrical Engineering

Rocznik: 2017 | Numer: Issue 91

Typ artykułu

artykuł naukowy

Język publikacji


Słowa kluczowe
  • high-level synthesis
  • residue number system
  • FPGA
  • C++ language
  • two's complement–to–residue converter

EN The work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is represented as the program in C++. The performed design experiments had to show whether the obtained structures of TCS/RNS converter are acceptable with respect to speed and hardware complexity. The other aim of the work was to examine whether it is enough to write the program in C++ with the use of basic arithmetic operators or bit–level description is necessary. Finally, we present the discussion of results of the TCS/RNS converter design in Xilinx Vivado HLS environment.

Strony (od-do)

143 - 154



Zaprezentowany na

Computer Applications in Electrical Engineering 2017, 10-11.04.2017, Poznań, Polska

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Punktacja MNiSW / czasopismo

9 [Ujednolicony wykaz czasopism naukowych 2013-2016]