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Chapter

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Title

Design for low test pattern counts

Authors

[ 1 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ 2 ] Dziekanat Wydziału Elektroniki i Telekomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Year of publication

2015

Chapter type

paper

Publication language

english

Keywords
EN
  • Design for testability
  • scan-based test
  • test data compression
Abstract

EN This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x – 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

Pages (from - to)

1 - 6

DOI

10.1145/2744769.2744817

URL

https://ieeexplore.ieee.org/document/7167321

Book

52nd ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, 8-12 June 2015

Presented on

52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 8-12.06.2015, San Francisco, United States

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