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Article

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Title

Test Time Reduction in EDT Bandwidth Management for SoC Designs

Authors

[ 1 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Year of publication

2013

Published in

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal year: 2013 | Journal volume: vol. 32 | Journal number: no. 11

Article type

scientific article

Publication language

english

Keywords
EN
  • bandwidth management
  • embedded deterministic test
  • scan-based test
  • test access mechanism
  • test application time
  • test compression
  • test scheduling
Abstract

EN This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

Pages (from - to)

1776 - 1786

DOI

10.1109/TCAD.2013.2263038

URL

https://ieeexplore.ieee.org/document/6634561

Ministry points / journal

25

Impact Factor

1,203

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