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Article

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Title

Logic BIST with capture-per-clock hybrid test points

Authors

[ 1 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Scientific discipline (Law 2.0)

[2.3] Information and communication technology

Year of publication

2019

Published in

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal year: 2019 | Journal volume: vol. 38 | Journal number: no. 6

Article type

scientific article

Publication language

english

Keywords
EN
  • design for testability
  • embedded test
  • logic built-in self-test (LBIST)
  • scan-based testing
  • test points
Pages (from - to)

1028 - 1041

DOI

10.1109/TCAD.2018.2834441

URL

http://ieeexplore.ieee.org

Ministry points / journal

100

Ministry points / journal in years 2017-2021

100

Impact Factor

2,168

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