SIS PUT | Jędrzej Solecki

Scientific Information System of the Poznań University of Technology

PL EN

Main page / People / Jędrzej Solecki

Phd student

All publications

Jędrzej Solecki

Articles | Chapters | Dissertation | IP outcomes

1.

Time and Area Optimized Testing of Automotive ICs / Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski (WIiT), Elham Moghaddam, Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WIiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2021, vol. 29, no. 1, p. 76-88

Scientific article 100.0 2.775
2.

Logic BIST with capture-per-clock hybrid test points / Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WEiT), Justyna Zawada // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2019, vol. 38, no. 6, p. 1028-1041

Scientific article 100.0 2.168
3.

Star-EDT: Deterministic on-chip scheme using compressed test patterns / Grzegorz Mrugalski, Janusz Rajski, Łukasz Rybak, Jędrzej Solecki, Jerzy Tyszer (WEiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2017, vol. 36, no. 4, p. 683-693

Scientific article 25.0 2.089
4.

Trimodal scan-based test paradigm / Jerzy Tyszer (WEiT), Grzegorz Mrugalski, Janusz Rajski, Jędrzej Solecki, Chen Wang // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2017, vol. 25, no. 3, p. 1112-1125

Scientific article 30.0 1.744
5.

Low-Power Programmable PRPG With Test Compression Capabilities / Michał Filipek (WEiT), Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jędrzej Solecki (WEiT), Jerzy Tyszer (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2015, vol. 23, no. 6, p. 1063-1076

Scientific article 30.0 1.245

All ARTICLES

1.

Test Time and Area Optimized BrST Scheme for Automotive ICs / Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham Moghaddam, Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WEiT) // W: IEEE International Test Conference (ITC 2019): IEEE, 2019

Chapter in monograph / paper 20.0 70.0
2.

Staggered ATPG with capture-per-cycle observation test points / Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jędrzej Solecki, Jerzy Tyszer (WEiT) // W: IEEE 36th VLSI Test Symposium (VTS 2018): IEEE, 2018

Chapter in monograph / paper 20.0
3.

Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points / Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WEiT), Justyna Zawada (WEiT) // W: 2017 IEEE INTERNATIONAL TEST CONFERENCE (ITC) - New York, NY, USA : IEEE, 2017

Chapter in monograph / paper 20.0 70.0
4.

A deterministic BIST scheme based on EDT-compressed test patterns / Grzegorz Mrugalski, Janusz Rajski, Łukasz Rybak, Jędrzej Solecki (WEiT), Jerzy Tyszer (WEiT) // W: IEEE International Test Conference (ITC), Anaheim, CA, 6-8 October 2015: IEEE, 2015 - p. 1-8

Paper
5.

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm / Grzegorz Mrugalski, Janusz Rajski, Jędrzej Solecki (WEiT), Jerzy Tyszer (WEiT) // W: IEEE 24th Asian Test Symposium (ATS), Mumbai, India, 22-25 November 2015: IEEE, 2015 - p. 19-24

Paper

All CHAPTERS

1.

Testing digital integrated circuits with novel low power high fault coverage techniques and a new scan architecture / Jędrzej Solecki (WEiT) / prom. Jerzy Tyszer (WEiT), rev. Sybille Hellebrand, Andrzej Kraśniewski - Poznań, Polska, 2015 - 104 s.

Dissertation

1.

Test Application Time Reduction Using Capture-Per-Cycle Test Points / Janusz Rajski, Sylwester Milewski, Nilanjan Mukherje, Jędrzej Solecki, Jerzy Tyszer (WIiT), Justyna Zawada // 0100

Invention
2.

Deterministic Built-In Self-Test / Grzegorz Mrugalski, Janusz Rajski, Łukasz Rybak, Jędrzej Solecki, Jerzy Tyszer (WIiT) // 0085

Invention
3.

Scan chain stitching for test-per-clock / Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WIiT), Grzegorz Mrugalski // 0102

Invention

All OUTCOMES

System created by Poznań University of Technology and Poznan Supercomputing and Networking Center

Scientific Information System of the Poznań University of Technology

Phd student

Jędrzej Solecki

Articles (6)

Chapters (5)

Dissertation

IP outcomes (3)