A deterministic BIST scheme based on EDT-compressed test patterns
[ 1 ] Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ 2 ] Katedra Radiokomunikacji, Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee
2015
paper
english
EN The paper presents a novel deterministic built-in self-test (BIST) scheme. The proposed solution seamlessly integrates with on-chip EDT-based decompression logic and takes advantage of two key observations: (1) specified positions of ATPG-produced test cubes are typically clustered within a single or a few scan chains for a small number of successive scan shift cycles, (2) only a small fraction of the specified positions are necessary to detect a fault, and most of the remaining ones have several alternatives that can be obtained by inverting preselected scan slices (all scan cells within a given cycle). The proposed approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed logic BIST scheme and are reported herein.
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