Minimal area test points for deterministic patterns
[ 1 ] Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee
2016
paper
english
- flip-flops
- measurement
- logic gates
- circuit faults
- silicon
- automatic test pattern generation
- signal resolution
EN Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.
1 - 7