2017

chapter in monograph / paper

english

EN This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes. Alternatively, one may consider applying a much larger number of vectors within the same time interval. Although the new scheme may resemble traditional BIST logic, it is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid test points that creates this new synergistic LBIST paradigm. The hybrid observation points, inserted at the most suitable locations, capture faulty effects every shift cycle into dedicated flip-flops that form separate scan chains. Their content is gradually shifted into a compactor, which is shared with the remaining scan chains that still deliver test responses captured once the entire test pattern has been shifted-in. Experimental results obtained for industrial designs illustrate feasibility of the proposed BIST scheme in terms of test time, test coverage, and area overhead, and they are reported herein.

1 - 9

10.1109/TEST.2017.8242036

https://ieeexplore.ieee.org/document/8242036

2017 IEEE International Test Conference (ITC)

48th IEEE International Test Conference, ITC 2017, 31.10.2017 - 02.11.2017, Fort Worth, USA

20

70

WoS (15)