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Chapter

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Title

Minimal area test points for deterministic patterns

Authors

[ 1 ] Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee

Year of publication

2016

Chapter type

paper

Publication language

english

Keywords
EN
  • flip-flops
  • measurement
  • logic gates
  • circuit faults
  • silicon
  • automatic test pattern generation
  • signal resolution
Pages (from - to)

1 - 7

DOI

10.1109/TEST.2016.7805825

Book

2016 IEEE International Test Conference (ITC)

Presented on

2016 IEEE International Test Conference (ITC), 15-17.11.2016, Houston, USA

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