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If it takes too long to generate, you can limit the data by, for example, reducing the range of years.

Chapter

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Title

Test point insertion in hybrid test compression/LBIST architectures

Authors

[ 1 ] Wydział Elektroniki i Telekomunikacji, Politechnika Poznańska | [ P ] employee | [ D ] phd student

Year of publication

2016

Chapter type

paper

Publication language

english

Keywords
EN
  • logic gates
  • circuit faults
  • built-in self-test
  • system-on-chip
  • silicon
  • automotive engineering
  • discrete fourier transforms
Pages (from - to)

1 - 10

DOI

10.1109/TEST.2016.7805826

Book

2016 IEEE International Test Conference (ITC)

Presented on

2016 IEEE International Test Conference (ITC), 15-17.11.2016, Houston, USA

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