Title
Embedded deterministic test for low cost manufacturing test
Authors
[ 1 ] Instytut Elektrotechniki i Telekomunikacji (IEt), Wydział Elektryczny, Politechnika Poznańska | [ P ] employee
Year of publication
2002
Chapter type
paper
Publication language
english
Abstract
EN This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.
Pages (from - to)
301 - 310
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