1.

LBIST for Automotive ICs with Enhanced Test Generation / Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Łukasz Rybak, Jerzy Tyszer (WIiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2022, vol. 41, no. 7, p. 2290-2300

Scientific article 100 2,9

2.

Time and Area Optimized Testing of Automotive ICs / Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski (WIiT), Elham Moghaddam, Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WIiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2021, vol. 29, no. 1, p. 76-88

Scientific article 100 2,775

3.

Deterministic Stellar BIST for Automotive ICs / Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer (WIiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2020, vol. 39, no. 8, p. 1699-1710

Scientific article 100 2,807

4.

Logic BIST with capture-per-clock hybrid test points / Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jędrzej Solecki, Jerzy Tyszer (WEiT), Justyna Zawada // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2019, vol. 38, no. 6, p. 1028-1041

Scientific article 100 2,168

5.

Hardware Protection via Logic Locking Test Points / Michael Chen, Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT), Justyna Zawada (WEiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2018, vol. 37, no. 12, p. 3020-3030

Scientific article 25 2,402

6.

Embedded Deterministic Test Points / Cesar Acero, Derek Feltham, Yingdi Liu, Elham Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer (WEiT), Justyna Zawada (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2017, vol. 25, no. 10, p. 2949-2961

Scientific article 30 1,744

7.

On New Test Points for Compact Cell-Aware Tests / Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer (WEiT), Justyna Zawada (WEiT) // IEEE Design & Test - 2016, vol. 33, iss. 6, p. 7-14

Scientific article 30 1,366

8.

Isometric Test Data Compression / Amit Kumar, Mark Kassab, Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer (WEiT), Chen Wang // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2015, vol. 34, no. 11, p. 1847-1859

Scientific article 25 1,181

9.

Low-Power Programmable PRPG With Test Compression Capabilities / Michał Filipek (WEiT), Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jędrzej Solecki (WEiT), Jerzy Tyszer (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2015, vol. 23, no. 6, p. 1063-1076

Scientific article 30 1,245

10.

Scan test bandwidth management for ultra-large-scale multicore architectures / Wu-Tung Cheng, Yan Dong, Grady Gilles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2015, vol. 23, no. 6, p. 1050-1062

Scientific article 30 1,245

11.

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures / Wu-Tung Cheng, Yan Dong, Grady Gilles, Yu Huang, Jakub Janicki (WEiT), Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Very Large Scale Integration (VLSI) Systems - 2015, vol. 23, no. 6, p. 1050-1062

Scientific article 30 1,245

12.

On deploying scan chains for data storage in test compression environment / Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Design and Test of Computers - 2013, vol. 30, iss. 1, p. 68-76

Scientific article 30

13.

Test Time Reduction in EDT Bandwidth Management for SoC Designs / Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2013, vol. 32, no. 11, p. 1776-1786

Scientific article 25 1,203

14.

EDT Bandwidth Management in SoC Designs / Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2012, vol. 31, no. 12, p. 1894-1907

Scientific article 1,093

15.

High performance dense ring generators / Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WEiT) // IEEE Transactions on Computers - 2006, vol. 55, no. 1, p. 83-87

Scientific article 1,426

16.

Embedded deterministic test / Janusz Rajski, Jerzy Tyszer (WE), Mark Kassab, Nilanjan Mukherjee // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - 2004, vol. 23, iss. 5, p. 776-792

Scientific article 0,913

17.

Embedded deterministic test for low cost manufacturing / Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer (WE), Jun Qian // IEEE Design and Test of Computers - 2003, vol. 20, iss. 5, p. 58-66

Scientific article

18.

Testing schemes for FIR filter structures / Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer (WE) // IEEE Transactions on Computers - 2001, vol. 50, iss. 7, p. 674-688

Scientific article